DFT Engineer

About the Role

Key Responsibilities

• Responsible for DFT Design for Testability aspects of ASIC Design and ensuring thorough understanding of digital design concepts.
• Knowledgeable in VHDL, Verilog, or SystemVerilog RTL coding and highly proficient in DFT methodologies.
• Operate in a team environment and collaborate across different teams to accomplish project goals.
• Generate test patterns, analyze, and debug test failures.
• Work with test engineers to implement ATPG vectors on tester hardware.

Requirements

• Bachelor's degree in Electrical or Computer Engineering with 8 years of experience, or a Master's degree with 6 years of experience.
• U.S. Citizenship is required.
• Experience in the full product life cycle of ASIC Design.
• Experience with Cadence and/or Mentor test insertion and ATPG tools.
• Experience with hierarchical scan testing IEEE-1500 and/or IEEE-1687 test compression, JTAG IEEE-1149.1 and IEEE-1149.6, AC JTAG.
• Experience with memory BIST and logic BIST.
• Proficiency in HDL (VHDL/Verilog/SystemVerilog) and scripting languages such as Tcl, Python, or Perl.
• Effective communication and presentation skills, with high proficiency in technical problem solving.

Nice to Have

• Master's Degree in Electrical or Computer Engineering.
• Expertise in using Cadence Modus DFT tools.
• Knowledge of Synthesis, PR, and Static Timing Analysis.

Qualifications

• Bachelor's degree in Electrical or Computer Engineering.
• 8 years of experience with a Bachelor's degree or 6 years with a Master's degree.

Benefits & Perks

• Pay range of $80.00 - $90.00/hr.
• Medical, dental & vision insurance.
• Critical Illness, Accident, and Hospital coverage.
• 401(k) Retirement Plan with pre-tax and Roth post-tax contributions.
• Life Insurance (Voluntary Life & AD&D for employee and dependents).
• Short and long-term disability coverage.
• Health Spending Account (HSA).
• Transportation benefits.
• Employee Assistance Program.
• Time Off/Leave (PTO, Vacation, Sick Leave).